`timescale 1ns/1ns

module ADDSUB_16_tb (

);
    reg [15:0] a;
    reg [15:0] b;
    reg c_in;
    wire [3:0] G;
    wire [3:0] P;
    wire [15:0] s;
    wire c_out;
    wire [15:0] check;

    initial begin
        a = 16'd2;
        b = 16'd1;
        c_in = 0;
        #2
        a = 16'd8;
        b = 16'd8;
        #2
        a = {$random} % 65536;
        b = {$random} % 65536;
        #2
        a = {$random} % 65536;
        b = {$random} % 65536;
        #2
        a = {$random} % 65536;
        b = {$random} % 65536;
        #2
        a = 16'd120;
        b = 16'd230;
        #2
        a = 16'd2000;
        b = 16'd200;
    end

    assign check = a + b;



    ADDSUB_16 u_ADDSUB_16(
    	.clk  (clk  ),
        .RST  (1'b1  ),
        .a    (a    ),
        .b    (b    ),
        .c_in (c_in ),
        .s    (s    )
    );
    
    
endmodule